1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device.
2. Description of the Related Art
A dynamic sense amplifier can be configured by using a same type of transistor as that of a usual logic circuit and can be operated in a same power source voltage. Thus, the dynamic sense amplifier has a feature that its chip area can be reduced to a small size. However, the dynamic sense amplifier operates erroneously unless the operation is started after a sufficient differential voltage (signal voltage) equal to or larger than an operational margin of the sense amplifier is generated on an input side of the sense amplifier (an input end of a bit line voltage and an input end of a reference voltage). Thus, in order to avoid the erroneous operation, it is necessary to wait until the generation of the sufficient differential signal voltage. However, the wait time depends on the memory cell characteristic that is varied with deviation in a manufacturing process and the change in an operational temperature. For this reason, in order to avoid the reduction in the production yield, a timing design must be typically carried out to be adaptive to the worst memory cell characteristic. Thus, even if the characteristic of the manufactured memory cell is improved, an access time is not improved (a high speed operation cannot be attained) unless the timing design is changed. That is, attainment of both the high manufacturing yield and the high speed operation was difficult.
Conventionally, Japanese Laid Open Patent Application (JP-P 2001-357687A, a first conventional example) and U.S. Pat. No. 6,128,226 (a second conventional example) are known as a technique for generating a sense amplifier activation or deactivation signal to carry out a control so that the operation timing of the dynamic sense amplifier becomes optimal.
In the first conventional example, a non-volatile semiconductor memory device is disclosed. In this non-volatile semiconductor memory device, a reference cell is prepared which is set to an intermediate threshold voltage between a written state and an erased state in a memory cell. A bit line and a reference bit line are precharged in advance by a precharging circuit. The voltages of the bit line and the reference bit line are reduced based on the states of the memory cell and the reference cell, respectively. When the voltages of the bit line and the reference bit line become sufficiently low voltages, the outputs of the sense amplifier and the reference cell sense amplifier are respectively inverted. However, the threshold voltage of the reference cell is higher than the threshold voltage of the memory cell in the erased state. For this reason, when the memory cell is in the erased state, the output of the sense amplifier is inverted earlier than the reference cell sense amplifier. On the other hand, when the memory cell is in the written state, even if the output of the reference cell sense amplifier is inverted, the output of the sense amplifier is not still inverted. Thus, the timing when the reference cell sense amplifier is inverted is defined as the timing of a sensing completion. Consequently, a read operation from the memory cell is normally carried out. The timing of the sensing start of the sense amplifier corresponds to the completion of the precharging of the bit line.
In the second conventional example, an apparatus is disclosed for sensing a signal from a memory cell in a memory cell array. In this apparatus, a sense amplifier compares a bit line voltage (Vcell-erased or Vcell-programmed) read from the memory cell with a reference voltage to determine a data stored in the memory cell. The determination of the data is carried out at a timing of a sense amplifier activation signal φ2. The reference voltage is generated by a reference voltage generating circuit (Reference Unit). The reference voltage is obtained when the current flowing through the reference cell which has the same structure as the memory cell and is in an erased state charges the parasitic capacitance equal to two or three times of that of the bit line. The sense amplifier activation signal φ2 is generated through the comparison between a voltage Vtimer, which is obtained when the current flowing through the timing generating reference cell that has the same structure as the memory cell and is in the erased state charges a capacitance Ct, and a voltage Vdc-ref which is a constant voltage.
However, the non-volatile semiconductor memory device of the first conventional example requires the dedicated reference cell in order to generate the timing when the sense amplifier is deactivated. Also, the reference cell is required to be set to a dedicated intermediate potential. For this reason, the dedicated writing circuit, verifying circuit and sequence circuit are required. That is, the circuit configuration becomes complicated. Also, the timing when the data is determined is the timing when a control signal indicating the timing of a sensing completion is generated. This is because the timing is determined based on the magnitude of the on-current of the reference cell, namely, the reduction rate of the bit line voltage. That is, the operation speed of the sensing is determined based on the on-current of the reference cell whose voltage is set to be higher than the threshold voltage of the cell in the erased state. For this reason, the read operation speed becomes slow.
On the other hand, the apparatus in the second conventional example requires the dedicated reference cell in order to generate the timing for the activation or deactivation of the sense amplifier. Also, the timing generation reference cell does not exist in the memory cell array. For this reason, the manufacturing variation to the timing generation reference cell differs from that of the memory cell. That is, although the capacitance associated with the memory cell is a parasitic capacitance on the bit line, the timing generating circuit charges a capacitor of the capacitance Ct. Thus, it is difficult to generate the optimal timing in accordance with the process dependent deviation and the temperature dependent variation. Similarly, the reference cell of the reference voltage generating circuit does not exist in the memory cell array. For this reason, the manufacturing variation received by the reference cell differs from that of the memory cell. Therefore, when the sense amplifier activation signal φ2 is generated, there is no insurance that the sufficient differential signal voltage (the difference between the bit line voltage and the reference voltage) is obtained.